Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies

Bit-serial multiply-accumulate units (MACs) play a crucial role in various hardware accelerator applications, including deep learning, image processing, and signal processing. Despite the advantages of bit-serial MACs, such as small footprint, full utilization, high frequency, their serial nature can lead to latency potentially compromised performance. This study investigates potential solutions by applying Booth encoding multipliers within MACs enhance area power efficiencies. We present two types based on radix-2 radix-4 multipliers, respectively. Their performance is assessed through simulations synthesis results, demonstrating benefits proposed approach. The MAC improves efficiencies compared original MAC. Operating at TSMC 90 nm 150 MHz, our design exhibits remarkable 96.39% reduction area-power-product (APP). Moreover, prototype verification Xilinx Kintex-7 FPGA proved successful. solution offers significant energy efficiency, reduction, APP, making it promising candidate for next-generation accelerators offline inference, low-power devices, other applications.